1. Field of the Invention
This invention relates to the field of system management in multi-node environments.
2. Description of the Related Art
System Management mode (SMM) is a special mode used in Intel compatible computer systems in which a special memory segment is used to store information and execute instructions without the “knowledge” of the operating system, i.e., in the background. This mode is typically used to handle hardware specific functions, and is used today in a high-end server systems for management of reliability related functions such as memory scrubbing and error handling. A primary function of SMM is the checking/monitoring of the memory and I/O subsystems within the computer.
SMM offers great flexibility for computer designers; however, it can also cause unintended problems if the execution time of this management code takes too much time away from the operating system. This problem arises in symmetric multiprocessing (SMP) machines and can become particularly severe in large multi-chassis or multi-node computers (the terms “node” and “chassis” are used interchangeably herein).
SMP is a computer architecture that provides fast performance by making multiple CPUs available to complete individual processes simultaneously. Unlike asymmetrical processing, any idle processor can be assigned any task, and additional CPUs can be added to improve performance and handle increased loads. A typical SMP configuration utilizes four CPUs and is referred to as a “four-way SMP system”. In prior art four-way SMP systems, the SMM is configured so that one of the four CPUs accesses the SMM memory segment and controls and manages the SMM processes for the entire chassis. This is referred to as “Scheme 1 SMM” herein.
Recognizing that the timely checking of memory and I/O subsystems is highly desirable, an improvement was developed whereby all four CPUs can be utilized simultaneously (i.e., in parallel), thereby minimizing the delay. In this configuration, the SMM memory segment is partitioned so that each CPU can be allocated its task from the SMM code to perform an expeditious check on the memory and I/O subsystems. This is referred to herein as “Scheme 2 SMM”.
A multi-chassis or multi-node SMP computer is configured by the interconnection of multiple computer chassis or nodes in a manner such that they act in concert as a single computer entity. The nodes of a multi-node computer system can be typically assembled from four-way SMP machines. Particularly in the case where the multiple nodes are interconnected to comprise large SMP machines, such as eight-way or 16-way SMP machines, the SMM processes and control and management thereof present significant delay and/or performance issues. Specifically, if Scheme 1 SMM processing is utilized, the size of memory and I/O subsystems to be checked using SMM multiplies, essentially increases 100% for each additional node. For example, in a two node computer system the single CPU assigned the task of performing the checking/managing operations must do so, not only for the memory and I/O subsystems within its own node, but also for the memory and I/O subsystems in the second node. Obviously, the more nodes there are in the multi-node computer system, the greater the number (or size) memory and I/O subsystems that will need to be checked by the single CPU assigned this task.
If Scheme 2 SMM processing is utilized, while it is true that all of the memory and I/O subsystems will be checked more quickly than in Scheme 1, it does not take advantage of the node architecture, since every CPU's task will be stored in and execute from the same base SMM resource space, hence creating inefficiencies in interconnection traffic, control and reporting, and root node SMM memory space utilization.
Accordingly, it would be desirable to have a way to efficiently utilize SMM processing in a multi-node system.